AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
-
Updated
Dec 19, 2024 - SystemVerilog
#
asic
Here are 37 public repositories matching this topic...
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
cmake asic fpga cpp verification rtl verilog xilinx vivado systemverilog systemc unit-tests hdl modelsim uvm verilator quartus testing-rtl
-
Updated
Nov 25, 2019 - SystemVerilog
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
-
Updated
Nov 22, 2024 - SystemVerilog
Repository gathering basic modules for CDC purpose
-
Updated
Dec 31, 2019 - SystemVerilog
A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
-
Updated
Dec 17, 2024 - SystemVerilog
Simple single-port AXI memory interface
-
Updated
Jun 7, 2024 - SystemVerilog
An open source, parameterized SystemVerilog digital hardware IP library
asic fpga hardware ip verilog systemverilog hardware-designs hardware-libraries hdl digital-design asic-library fpga-library
-
Updated
May 26, 2024 - SystemVerilog
RISCV CPU implementation in SystemVerilog
asic fpga assembler riscv verilog systemverilog fpga-soc risc-v rv32i crossbar axi4 axi4-protocol asic-design riscv-cpu
-
Updated
Oct 8, 2024 - SystemVerilog
SystemVerilog Logger
-
Updated
Nov 14, 2022 - SystemVerilog
Implementation of a binary search tree algorithm in a FPGA/ASIC IP
asic fpga ip verilog binary-tree systemverilog binary-trees bst fpga-accelerator bstree asic-design svut
-
Updated
Sep 5, 2021 - SystemVerilog
RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
-
Updated
Sep 21, 2023 - SystemVerilog
6-stage in-order dual-issue superscalar risc-v cpu with floating point unit
-
Updated
Dec 23, 2024 - SystemVerilog
ASIC Design lab. Pipelined, Cached, Multicore MIPS Processor
-
Updated
Aug 23, 2017 - SystemVerilog
Benchmark fo state-of-the-art Precision Scalable MAC Arrays (PSMAs)
asic neural-networks precision-scalable-circuits neural-accelerators configurable-circuits multiply-accumulate mac-array-utilization
-
Updated
Nov 2, 2021 - SystemVerilog
SystemVerilog files for simulating a complete Game Boy system with DMG-CPU B chip
nintendo asic gameboy simulation electronics verilog chip systemverilog game-boy icarus-verilog dmg-001 dmg-cpu
-
Updated
Jun 15, 2024 - SystemVerilog
Improve this page
Add a description, image, and links to the asic topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the asic topic, visit your repo's landing page and select "manage topics."