A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
XCrypto: a cryptographic ISE for RISC-V
Quickstart guide on Icarus Verilog.
💎 A 32-bit ARM Processor Implementation in Verilog HDL
A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.
🎞️ NoC router in Verilog with FIFO
🔮 A 16-bit MIPS Processor Implementation in Verilog HDL
Apache 2.0 licensed copy of the Xilinx Unisim library.
🌱 Icarus Verilog pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS
This project provide the necessary to run a env test a simple uart verilog using SystemC and running it on icarus verilog
RTL implementation of a MoldUPD64 receiver.
🔐 Hardware Implementation Of AES Algorithm in Verilog HDL
✨🐾✨ A Control System for Washing Machine in Verilog HDL
☎️ UART Communication Implementation in Verilog HDL
📍 A FIFO Memory Implementation in Verilog HDL
A simple up-down counter made using icarus verilog as a part of the Digital Design and Computer Organization course (UE18CS201) at PES University.
Implementation of Hopfield network using Verilog
🛠 A SDRAM controller in Verilog HDL
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