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11 | 11 | #define GET_BUS(msg) (((msg)->RDTR >> 4) & 0xFF) |
12 | 12 | #define GET_LEN(msg) ((msg)->RDTR & 0xF) |
13 | 13 | #define GET_ADDR(msg) ((((msg)->RIR & 4) != 0) ? ((msg)->RIR >> 3) : ((msg)->RIR >> 21)) |
14 | | -#define GET_BYTE(msg, b) (((int)(b) > 3) ? (((msg)->RDHR >> (8U * ((unsigned int)(b) % 4U))) & 0XFFU) : (((msg)->RDLR >> (8U * (unsigned int)(b))) & 0xFFU)) |
| 14 | +#define GET_BYTE(msg, b) (((int)(b) > 3) ? (((msg)->RDHR >> (8U * ((unsigned int)(b) % 4U))) & 0xFFU) : (((msg)->RDLR >> (8U * (unsigned int)(b))) & 0xFFU)) |
15 | 15 | #define GET_BYTES_04(msg) ((msg)->RDLR) |
16 | 16 | #define GET_BYTES_48(msg) ((msg)->RDHR) |
17 | 17 |
|
| 18 | +#define CAN_INIT_TIMEOUT_MS 500U |
| 19 | +#define CAN_NAME_FROM_CANIF(CAN_DEV) (((CAN_DEV)==CAN1) ? "CAN1" : (((CAN_DEV) == CAN2) ? "CAN2" : "CAN3")) |
| 20 | + |
18 | 21 | void puts(const char *a); |
19 | 22 |
|
20 | 23 | bool llcan_set_speed(CAN_TypeDef *CAN_obj, uint32_t speed, bool loopback, bool silent) { |
| 24 | + bool ret = true; |
| 25 | + |
21 | 26 | // initialization mode |
22 | 27 | register_set(&(CAN_obj->MCR), CAN_MCR_TTCM | CAN_MCR_INRQ, 0x180FFU); |
23 | | - while((CAN_obj->MSR & CAN_MSR_INAK) != CAN_MSR_INAK); |
24 | | - |
25 | | - // set time quanta from defines |
26 | | - register_set(&(CAN_obj->BTR), ((CAN_BTR_TS1_0 * (CAN_SEQ1-1)) | |
27 | | - (CAN_BTR_TS2_0 * (CAN_SEQ2-1)) | |
28 | | - (can_speed_to_prescaler(speed) - 1U)), 0xC37F03FFU); |
29 | | - |
30 | | - // silent loopback mode for debugging |
31 | | - if (loopback) { |
32 | | - register_set_bits(&(CAN_obj->BTR), CAN_BTR_SILM | CAN_BTR_LBKM); |
33 | | - } |
34 | | - if (silent) { |
35 | | - register_set_bits(&(CAN_obj->BTR), CAN_BTR_SILM); |
| 28 | + uint32_t timeout_counter = 0U; |
| 29 | + while((CAN_obj->MSR & CAN_MSR_INAK) != CAN_MSR_INAK){ |
| 30 | + // Delay for about 1ms |
| 31 | + delay(10000); |
| 32 | + timeout_counter++; |
| 33 | + |
| 34 | + if(timeout_counter >= CAN_INIT_TIMEOUT_MS){ |
| 35 | + puts(CAN_NAME_FROM_CANIF(CAN_obj)); puts(" set_speed timed out (1)!\n"); |
| 36 | + ret = false; |
| 37 | + break; |
| 38 | + } |
36 | 39 | } |
37 | 40 |
|
38 | | - // reset |
39 | | - register_set(&(CAN_obj->MCR), CAN_MCR_TTCM | CAN_MCR_ABOM, 0x180FFU); |
40 | | - |
41 | | - #define CAN_TIMEOUT 1000000 |
42 | | - int tmp = 0; |
43 | | - bool ret = false; |
44 | | - while(((CAN_obj->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (tmp < CAN_TIMEOUT)) tmp++; |
45 | | - if (tmp < CAN_TIMEOUT) { |
46 | | - ret = true; |
| 41 | + if(ret){ |
| 42 | + // set time quanta from defines |
| 43 | + register_set(&(CAN_obj->BTR), ((CAN_BTR_TS1_0 * (CAN_SEQ1-1)) | |
| 44 | + (CAN_BTR_TS2_0 * (CAN_SEQ2-1)) | |
| 45 | + (can_speed_to_prescaler(speed) - 1U)), 0xC37F03FFU); |
| 46 | + |
| 47 | + // silent loopback mode for debugging |
| 48 | + if (loopback) { |
| 49 | + register_set_bits(&(CAN_obj->BTR), CAN_BTR_SILM | CAN_BTR_LBKM); |
| 50 | + } |
| 51 | + if (silent) { |
| 52 | + register_set_bits(&(CAN_obj->BTR), CAN_BTR_SILM); |
| 53 | + } |
| 54 | + |
| 55 | + // reset |
| 56 | + register_set(&(CAN_obj->MCR), CAN_MCR_TTCM | CAN_MCR_ABOM, 0x180FFU); |
| 57 | + |
| 58 | + timeout_counter = 0U; |
| 59 | + while(((CAN_obj->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)) { |
| 60 | + // Delay for about 1ms |
| 61 | + delay(10000); |
| 62 | + timeout_counter++; |
| 63 | + |
| 64 | + if(timeout_counter >= CAN_INIT_TIMEOUT_MS){ |
| 65 | + puts(CAN_NAME_FROM_CANIF(CAN_obj)); puts(" set_speed timed out (2)!\n"); |
| 66 | + ret = false; |
| 67 | + break; |
| 68 | + } |
| 69 | + } |
47 | 70 | } |
48 | 71 |
|
49 | 72 | return ret; |
50 | 73 | } |
51 | 74 |
|
52 | | -void llcan_init(CAN_TypeDef *CAN_obj) { |
| 75 | +bool llcan_init(CAN_TypeDef *CAN_obj) { |
| 76 | + bool ret = true; |
| 77 | + |
53 | 78 | // Enter init mode |
54 | 79 | register_set_bits(&(CAN_obj->FMR), CAN_FMR_FINIT); |
55 | 80 |
|
56 | 81 | // Wait for INAK bit to be set |
57 | | - while(((CAN_obj->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)) {} |
58 | | - |
59 | | - // no mask |
60 | | - // For some weird reason some of these registers do not want to set properly on CAN2 and CAN3. Probably something to do with the single/dual mode and their different filters. |
61 | | - CAN_obj->sFilterRegister[0].FR1 = 0U; |
62 | | - CAN_obj->sFilterRegister[0].FR2 = 0U; |
63 | | - CAN_obj->sFilterRegister[14].FR1 = 0U; |
64 | | - CAN_obj->sFilterRegister[14].FR2 = 0U; |
65 | | - CAN_obj->FA1R |= 1U | (1U << 14); |
66 | | - |
67 | | - // Exit init mode, do not wait |
68 | | - register_clear_bits(&(CAN_obj->FMR), CAN_FMR_FINIT); |
69 | | - |
70 | | - // enable certain CAN interrupts |
71 | | - register_set_bits(&(CAN_obj->IER), CAN_IER_TMEIE | CAN_IER_FMPIE0 | CAN_IER_WKUIE); |
72 | | - |
73 | | - if (CAN_obj == CAN1) { |
74 | | - NVIC_EnableIRQ(CAN1_TX_IRQn); |
75 | | - NVIC_EnableIRQ(CAN1_RX0_IRQn); |
76 | | - NVIC_EnableIRQ(CAN1_SCE_IRQn); |
77 | | - } else if (CAN_obj == CAN2) { |
78 | | - NVIC_EnableIRQ(CAN2_TX_IRQn); |
79 | | - NVIC_EnableIRQ(CAN2_RX0_IRQn); |
80 | | - NVIC_EnableIRQ(CAN2_SCE_IRQn); |
81 | | -#ifdef CAN3 |
82 | | - } else if (CAN_obj == CAN3) { |
83 | | - NVIC_EnableIRQ(CAN3_TX_IRQn); |
84 | | - NVIC_EnableIRQ(CAN3_RX0_IRQn); |
85 | | - NVIC_EnableIRQ(CAN3_SCE_IRQn); |
86 | | -#endif |
87 | | - } else { |
88 | | - puts("Invalid CAN: initialization failed\n"); |
| 82 | + uint32_t timeout_counter = 0U; |
| 83 | + while(((CAN_obj->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)) { |
| 84 | + // Delay for about 1ms |
| 85 | + delay(10000); |
| 86 | + timeout_counter++; |
| 87 | + |
| 88 | + if(timeout_counter >= CAN_INIT_TIMEOUT_MS){ |
| 89 | + puts(CAN_NAME_FROM_CANIF(CAN_obj)); puts(" initialization timed out!\n"); |
| 90 | + ret = false; |
| 91 | + break; |
| 92 | + } |
89 | 93 | } |
| 94 | + |
| 95 | + if(ret){ |
| 96 | + // no mask |
| 97 | + // For some weird reason some of these registers do not want to set properly on CAN2 and CAN3. Probably something to do with the single/dual mode and their different filters. |
| 98 | + CAN_obj->sFilterRegister[0].FR1 = 0U; |
| 99 | + CAN_obj->sFilterRegister[0].FR2 = 0U; |
| 100 | + CAN_obj->sFilterRegister[14].FR1 = 0U; |
| 101 | + CAN_obj->sFilterRegister[14].FR2 = 0U; |
| 102 | + CAN_obj->FA1R |= 1U | (1U << 14); |
| 103 | + |
| 104 | + // Exit init mode, do not wait |
| 105 | + register_clear_bits(&(CAN_obj->FMR), CAN_FMR_FINIT); |
| 106 | + |
| 107 | + // enable certain CAN interrupts |
| 108 | + register_set_bits(&(CAN_obj->IER), CAN_IER_TMEIE | CAN_IER_FMPIE0 | CAN_IER_WKUIE); |
| 109 | + |
| 110 | + if (CAN_obj == CAN1) { |
| 111 | + NVIC_EnableIRQ(CAN1_TX_IRQn); |
| 112 | + NVIC_EnableIRQ(CAN1_RX0_IRQn); |
| 113 | + NVIC_EnableIRQ(CAN1_SCE_IRQn); |
| 114 | + } else if (CAN_obj == CAN2) { |
| 115 | + NVIC_EnableIRQ(CAN2_TX_IRQn); |
| 116 | + NVIC_EnableIRQ(CAN2_RX0_IRQn); |
| 117 | + NVIC_EnableIRQ(CAN2_SCE_IRQn); |
| 118 | + #ifdef CAN3 |
| 119 | + } else if (CAN_obj == CAN3) { |
| 120 | + NVIC_EnableIRQ(CAN3_TX_IRQn); |
| 121 | + NVIC_EnableIRQ(CAN3_RX0_IRQn); |
| 122 | + NVIC_EnableIRQ(CAN3_SCE_IRQn); |
| 123 | + #endif |
| 124 | + } else { |
| 125 | + puts("Invalid CAN: initialization failed\n"); |
| 126 | + } |
| 127 | + } |
| 128 | + return ret; |
90 | 129 | } |
91 | 130 |
|
92 | 131 | void llcan_clear_send(CAN_TypeDef *CAN_obj) { |
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