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Synthesize Verilog Modules

Create bcd_digital_clock.v #7

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Create bcd_digital_clock.v

Create bcd_digital_clock.v #7

Triggered via pull request February 15, 2025 00:47
@ewdlopewdlop
opened #25
ewdlop-patch-23
Status Failure
Total duration 8m 31s
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synthesis.yml

on: pull_request
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Process completed with exit code 2.