Skip to content

0.0.2
Compare
Choose a tag to compare
@jvanstraten jvanstraten released this 05 Sep 15:00
0.0.2
33baa91

NOTE: this release is broken; a couple template files were not included in the distribution. Use 0.0.3 instead.

Changes:

  • 33baa91 Commented out memory field config
  • e045cc4 Add alternative stream monitor example
  • 6dcab25 Fix typo in field suffix generation
  • 1bbe287 Fix typo in entity template
  • fd6e1a0 Fix bug in custom field with internals
  • ceb290c Fix missing end of sentence in documentation
  • efd91b3 Fix lint errors, implement memory field config
  • 389dd1b Add flattened bus mode for AXI fields
  • 29151b9 Implement AXI fields
  • ce81878 Add more tests for deferring fields + bugfixes
See more
  • 2b228d5 Add tests for blocking & deferring fields + fixes
  • b8cf2f9 Add tests for prot-based security + bugfixes
  • 7d51cf8 Add additional tests for field repetition
  • 7f3dbe7 Add tests for field repetition + bugfixes
  • 5a37596 Add interface check to all integration tests
  • d5cca05 Remove unused Parsed config loader
  • 23b80bf Add tests for subaddresses + bugfixes
  • 8705793 Remove dead VHDL code/TODO
  • 89f1e07 Add test for custom regs with internals + bugfixes
  • 12b0acc Minor bugfixes
  • 70086a9 Add test for custom field state
  • ace2b9e Save test case VHDL code when vhdeps launch fails
  • 0a10c8a Add tests for custom field ports + bugfixes
  • e4e67fe Add CLI tests for HTML and package generators
  • 1657467 Add tests for entity output using CLI + bugfixes
  • 475b333 Refactor examples
  • 0a33457 Fix bdist_wheel not including all files
  • 4278243 Clean up
  • 1dd7909 Fix generated component declaration
  • 7231690 Improve config test
  • 5b3ecac Fix cyclic import for version string
  • 0720f40 Print version info in all generated files
  • f9fdffa Add entity configuration options
  • 7c2f591 Add stream monitor example
  • 8db1c34 Add code generation for subaddresses
  • 7e2a150 Refactor field boilerplate template
  • 5714d87 Add initial tests for custom registers + bugfixes
  • 9319ce9 Implement custom behavior + unrelated bugfixes
  • 5900e0e Define configuration structure for custom behavior
  • ba6ea29 Refactor primitive behavior template
  • 20321ff Add tests for stream registers + bugfixes
  • f7cc798 Add tests for counter registers + bugfixes
  • 3a08081 Add tests for request registers + bugfixes
  • 2728a58 Add tests for flag registers + bugfixes
  • 30f6e74 Add tests for control registers
  • e7607e5 Add tests for status registers + bugfixes
  • 3478504 Add tests for constant registers + bugfixes
  • ce37ef2 Add tests for multi-word registers + bugfixes
  • 8a6e95b Add tests for addressing and conditions + bugfixes
  • 1313bf4 Add tests for interrupt fields + bugfixes
  • 41166c4 Add tests for interrupt sensitivity + bugfixes
  • 3809533 Fix version detection in setup.py
  • 78b4ffa Merge branch 'configuration-cleanup'
  • 7dc9e02 Update readme slightly
  • 89cd0c3 Merge pull request #1 from abs-tudelft/configuration-cleanup
  • e823a05 Fix CI pipeline
  • 327c482 Put stream interface signals in canonical order
  • 4522c00 Add tests for internals
  • 305236b Implement VHDL codegen for primitive and interrupt
  • 3bde23d Add 'wheel' to setup.py requirements
  • d3f5042 Minor changes to interrupt logic template
  • 117a83c Laid foundation for generating field logic again
  • 1f9e099 Complete VHDL generation excluding field logic
  • 44c70d2 Implement VHDL gen for internals + their I/O
  • a3be842 Improve HTML tooltip consistency
  • ef6cf5f Store blocks in address manager, expose signal map
  • 95f99c2 Add rudimentary way to indent templates
  • 5d888c2 Add option to make internal signals external
  • e835e32 Fix header levels in generated docs
  • ae33aa8 Add examples, clean up docs
  • 5e610f4 Refactor test directory
  • e75b014 Reintroduce register file testbench
  • 3f33473 Refactor VHDL generator so it doesn't crash
  • fab19da Refactored address decoder code
  • 2c1b153 Add support for overlapping addresses to decoder
  • f6d4f6c Tweaked HTML output
  • f13c6d1 Fix some unknown keys not detected
  • 6db4558 Implemented the majority of the HTML generator
  • cfe8763 Bugfixes, WIP on HTML target
  • 3727c77 Improve contextual errors
  • e90c0af Implement interrupts
  • 9eba405 Implement registers and blocks
  • 0dbb0f5 Refactor for name consistency
  • dde84dc Minor fixes/updates
  • fee3d5c Modify addressing.py for register builders
  • 1562f03 WIP on behavior code, add primitive
  • 64cdf72 WIP on core
  • f515b9e WIP on core
  • e7077ce WIP on core
  • 94705f6 Refactor mixins into own module, update AddressMgr
  • b32a925 WIP on new core code
  • bf11388 Update mdbook documentation
  • f1103c9 Added configuration keys for advanced addressing
  • d303a06 Refactored class names
  • bcb024c WIP
  • 9bb298a More refactoring
  • f9447d0 Add basic integration test
  • f497d87 Refactor + clean slate: delete all outdated
  • 113a02f Re-add load/save API, perform basic tests manually
  • 2e9c56e WIP on docs and config file structure
  • 8452d18 WIP on docs and config file structure
  • 6aa39de WIP on docs and config file structure
  • 932b6d8 WIP on config file structure with new system
  • cb300c1 Finish mutability/protection of configurables
  • 680c988 Lots of refactoring in the config system
  • 37c6d24 WIP
  • 5dfe55d Added the last two configuration loaders
  • 856900a Refactor @configurable code into its own module
  • e0b9053 WIP cleaning up configuration code
  • a1188c9 WIP cleaning up configuration code
  • 553f26b Reorganize field logic submodules
  • b3f9d97 Add .noseids to .gitignore
  • 31a0518 Add tests for interrupt fields
  • 104e2d9 Improved concepts document
  • dbb723d Add internal signal support
  • 4b7c11a Add tests for flag and counter fields
  • c6393c4 Add more tests for primitive fields
  • 464327d Add tests for control registers
  • 99ec7b9 Add access method flags to ReadWriteCapabilities
  • b849608 Improve coverage of vhdmmio.vhdl.interface
  • 4f90f46 Add tests for metadata objects
  • ae8240b Improve command line help
  • 11903d2 Add badges to README
  • 8ba69d5 Refactor test cases, add tests to linter pass
  • d54677d Refactor unsecure (not a real word) to non-secure
  • e5e6bcb Have nose generate XML coverage and test results
  • a78f1f0 Add automatic version tagging, clean up setup.py
  • c04a227 Fix lint errors, improve docstrings
  • faa143b Add initial azure-pipelines file
  • d465fae Rename YAML file used for testing
  • 5b0463f Fix setup.py not installing template files
  • edd4d74 Prevent xdg-open from opening py script in browser
  • 18366a0 Rethink command-line interface
  • 6d8951a WIP on docs
  • 518132a Add CAPI action register file description
  • 027b30a Add script entry point to setup.py
  • 0ad6498 Rename AXI field signals for consistency
  • 9a6d98a Add basic/temporary CLI
  • bf1c7cf Improve template annotations and error messages
  • 5759406 Implement initial code for AXI fields
  • 8f1e0c2 Fix bugs in defer tag generation
  • 423f8c2 Update gitignore for Cobertura XML data
  • a55a4fe Add annotations for template coverage
  • 40f488b Add interactive testbench generator for validation
  • 3cd2b1c Prepare for AXI passthrough field
  • 8568f06 Add access privileges
  • c963012 Add subfield support
  • 4fbe7e4 Complete interrupt fields
  • 6be6fd7 Add interrupt fields
  • 4d9327e Add integration test
  • c0800a0 Finish templates for primitive fields
  • 96db3de Recreate irq logic and interfaces with new system
  • 6aa8d24 Slight cleanup
  • 6665567 Complete interface generator
  • a8ee603 WIP
  • e65706e WIP
  • 2582010 WIP
  • 3854d22 Added VHDL type abstraction layer
  • 7ea0318 Fixed regression
  • 0c91f43 WIP
  • 10da5eb WIP on VHDL generation
  • 25f8017 Restructured, tried to pacify linter somewhat
  • 9284928 Finished VHDL address match generator
  • e8645bb WIP
  • 093abfc WIP
  • 11a8640 Fixed VHDL compile errors
  • 9721a2b WIP on interrupt stuff
  • 600bcda WIP
  • 4f1b2ee WIP
  • 2da9b21 Finished core for now (no tests yet)
  • 96f77c2 WIP
  • 16db13d WIP on core class hierarchy
  • ab11a95 Allow template files to define their own blocks
  • c7e2e62 Apply formatting to all code, not just blocks
  • 249c18f Replace $ comment/wrapping markers with @
  • bcb8931 Allow comment blocks to be indented
  • 8d29b73 Minor changes to VHDL template
  • e2a885e Added VHDL code (untested) and a template engine
  • 7c1887b WIP on toplevel framework
  • 407fa0b Add brainstorming notes
  • 69accba Add pylint to setup.py
  • 6ff3cb2 Add framework for Python tests and code coverage

This list of changes was auto generated.

Assets 3
Loading