A digital safe designed in Vivado, which has a 4 digit decimal password, and is implemented on PYNQ-Z2 board and RPI-Logic board
-
Updated
Jul 1, 2024 - Tcl
#
vivado-simulator
Here are 3 public repositories matching this topic...
This repository contains a Verilog implementation of a 24-hour digital clock designed for FPGA platforms. The design displays hours, minutes, and seconds on a 7-segment display, providing a complete timekeeping solution that can be easily integrated into various FPGA development boards.
fpga simulation verilog synthesis vivado systemverilog fpga-soc verilog-hdl 7segment systemverilog-hdl digitalclock nexys4ddr fpga-programming vivado-simulator
-
Updated
Feb 28, 2025 - Tcl
Digital design fundamentals - a 3rd year CSE banchelor course in ITMO University
circuits system-verilog verilog-hdl digital-design spice-simulator vivado-simulator system-verification
-
Updated
Nov 25, 2024 - Tcl
Improve this page
Add a description, image, and links to the vivado-simulator topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the vivado-simulator topic, visit your repo's landing page and select "manage topics."